Defence Research And Development Organisation Tender

Work Description - Fpga Ip Core Development Setup

The Department of Defence Research and Development, a Central Government Ministry/Department, invites open tenders for FPGA IP CORE DEVELOPMENT SETUP. The Tender Reference Number is DLRL/26ATT011/LP, and the Tender ID is 2025_DRDO_746680_1. The work, categorized as Goods, is to be executed at DLRL, HYDERABAD, with a period of work of 180 days and a bid validity of 120 days. Key dates include document download starting and ending on 31-Dec-2025 02:00 PM and 20-Jan-2026 11:00 AM respectively, a bid submission window from 07-Jan-2026 09:00 AM to 20-Jan-2026 11:00 AM, and a bid opening date of 21-Jan-2026 11:00 AM. An Earnest Money Deposit (EMD) of ₹7,09,947 is required, payable to THE DIRECTOR DLRL, CHANDRAYANGUTTA at STATE BANK OF INDIA, KANCHANBAGH, HYDERABAD, and can be submitted through BG/ST or EMD Exemption is allowed. The tender documents, including specifications and a price bid template, are available for download. The tender fee is ₹0.00. Bidders must submit their tenders in two covers, one for Fee/PreQual/Technical documents and the other for the Finance/Price bid. The tender allows for withdrawal and preferential bidders. Permissible payment instruments are Bankers Cheque, Bank Guarantee, Demand Draft and FDR.