Shri Mata Vaishno Devi University Tender

Work Description - Supply, Installation, Training, Testing And Commissioning Of Machine Learning Based Fpga Kits For Ceinc Lab At School Of Electronics And Communication Engineering, Smvdu, Kakryal, Katra

SHRI MATA VAISHNO DEVI UNIVERSITY, a State Govt. and UT organization, invites open tenders for the Supply, Installation, Training, Testing, and Commissioning of Machine Learning Based FPGA Kits for the CEINC Lab at the School of Electronics and Communication Engineering (SoECE), SMVDU, Kakryal, Katra. This tender, referenced as SMVDU/SoECE/Tenders/25/39, falls under the Goods category, specifically Electronics Equipment. Interested bidders must submit a Tender Fee of ₹1000 and an Earnest Money Deposit (EMD) of ₹20000. The ePublished Date is December 18, 2025, at 04:00 PM, coinciding with both the Document Download Start Date and the Bid Submission Start Date. The Document Download End Date and Bid Submission End Date are both January 5, 2026, at 05:00 PM. Bids will be opened on January 6, 2026, at 11:00 AM. All inquiries should be directed to the HOD SoECE, C Block SMVDU.