Mixed Signal Soc Based On Risc V And Analog Front End Asic

Work Description - Mixed Signal Soc Based On Risc-v And Analog Front-end Asic

The Department of Defence Research and Development, a Central Government Ministry/Department, invites open tenders for an Expression of Interest (EOI) related to a "Mixed Signal SoC based on RISC-V AND Analog Front-end ASIC" under Tender Reference Number RCI/ASIC/EOI/001. The tender, categorized as Goods, is being managed by S S REDDY KUMAR, RCI, DCMM, HYDERABAD. Key dates include a document download and bid submission start date of May 5th, 2026, at 6:00 PM, and an end date of June 8th, 2026, at 10:00 AM. The bid opening is scheduled for June 9th, 2026, at 10:30 AM. A pre-bid meeting is scheduled for May 26th, 2026, at 10:30 AM in the Conference Hall, DCMM, RCI, Hyderabad. The tender is single-cover and requires submission of technical and financial details. No EMD or Tender Fee is applicable. The bid validity is 180 days. Interested parties are encouraged to download the tender documents, including Tendernotice_1.pdf, NDA.pdf, EOI.pdf, and PREBID.pdf for comprehensive details.