Indian Institute Of Technology Tender

Work Description - 10 Gbps Ldpc Encoder-decoder Fpga Solution

The Director of the Indian Institute of Technology (IIT) Delhi, a Central Government Ministry/Department, invites open tenders for the procurement of a 10 Gbps LDPC Encoder-Decoder FPGA Solution. The tender reference number is IITD/COPH(SP-5097)/2025 and the Tender ID is 2025_IIT_874003_1. This is a "Buy" type contract for goods classified under Electrical Goods/Equipment. Bidding will be conducted in two covers. Cover 1 requires submission of Compliance Sheet, Organization Declaration, List of organizations/ clients where the same products have been supplied, Technical supporting documents, Previous Supply Order, OEM certificate, Certificate- Bidder Not from/ from Country sharing Land border with India, Declaration of Local Content, Bid Security Undertaking in lieu of EMD in .pdf formats. Cover 2 requires the price bid in .xls format. The document download and bid submission start date is August 20, 2025, at 03:35 PM, and the end date for both is September 17, 2025, at 03:00 PM. The bid opening date is September 18, 2025, at 03:00 PM. No EMD or Tender Fee is applicable for this tender. The successful bidder must complete the work within 112 days, and the bid validity period is 120 days. The tender inviting authority is Prof. Abhishek Dixit, located at Photonics Lab-303, BSTTM, IIT Delhi, New Delhi-110016.