FPGA and Processor Based PCB Realization and End-to-End Testing Services
- Opening DateNov 04, 2026
- Closing DateNov 06, 2026
- Tender Amount Refer Document
Tender Overview
| Tender Title | FPGA and Processor Based PCB Realization and End-to-End Testing Services | ||
| Tender ID | 2026_ISRO_856229_1 | Tender Reference Number | VSSC/PURCHASE UNIT II (AVN)/VS202600159201 |
| Tender Type | Limited. | ||
| Tender Opening Date | 2026-11-04 02:15 PM | Tender Closing Date | 2026-11-06 02:00 PM |
| Tender Value | Refer Document | Tender Location | Vssc Trivandrum , Thiruvananthapuram , Kerala |
| Tender Category | Goods | Product Category | Electrical and Electronics Tenders, Electronics Equipment Tenders |
- Tender TitleFPGA and Processor Based PCB Realization and End-to-End Testing Services
- Tender ID2026_ISRO_856229_1
- Tender Reference NumberVSSC/PURCHASE UNIT II (AVN)/VS202600159201
- Tender TypeLimited.
- Tender Opening Date2026-11-04 02:15 PM
- Tender Closing Date2026-11-06 02:00 PM
- Tender Value Refer Document
- Tender LocationVssc Trivandrum,Thiruvananthapuram, Kerala
- Tender CategoryGoods
- Product CategoryElectrical and Electronics Tenders, Electronics Equipment Tenders
Important Dates
| ePublished Date | 2026-11-04 02:15 PM | Bid Opening Date | 2026-11-06 02:30 PM |
| Document Download Start Date | 2026-11-04 02:15 PM | Document Download End Date | 2026-11-06 02:00 PM |
| Bid Submission Start Date | 2026-11-04 02:15 PM | Bid Submission End Date | 2026-11-06 02:00 PM |
| Clarification start Date | 2026-11-04 02:15 PM | Clarification End Date | 2026-11-06 02:00 PM |
| Bid Validity Period (in Days) | 90 |
- ePublished Date 2026-11-04 02:15 PM
- Bid Opening Date2026-11-06 02:30 PM
- Document Download Start Date2026-11-04 02:15 PM
- Document Download End Date2026-11-06 02:00 PM
- Clarification End Date2026-11-04 02:15 PM
- Clarification End Date2026-11-06 02:00 PM
- Bid Submission Start Date2026-11-04 02:15 PM
- Bid Validity Period (in Days)90
Cost Specification
| Tender Fee | Refer document |
| EMD (Earnest Money Deposit) | Refer document |
| EMD Fee Type | Fixed |
| Payment Instruments/Mode | Not Applicable |
Tender Description
Work Description - End To End Realization And Testing Of Fpga/processor Based Pcb
This tender, with reference number VSSC/PURCHASE UNIT II (AVN)/VS202600159201, is issued by the Indian Space Research Organisation (ISRO) for the "END TO END REALIZATION AND TESTING OF FPGA/PROCESSOR BASED PCB". This is a limited tender categorized under Goods, with a focus on Miscellaneous Goods. The tender is being invited by the SENIOR PURCHASE AND STORES OFFICER, located at the Purchase Unit-II, RFF Area, VSSC, ISRO, P.O., Trivandrum-695022. Interested parties can download tender documents from 04-Nov-2026 at 02:15 PM until 06-Nov-2026 at 02:00 PM. Bid submissions can commence on 04-Nov-2026 at 02:15 PM and must conclude by 06-Nov-2026 at 02:00 PM, with the bid opening scheduled for 06-Nov-2026 at 02:30 PM. Notably, there is no Tender Fee or Earnest Money Deposit (EMD) required for this tender. The work is to be carried out at VSSC Trivandrum.
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Tender Contact Details
| Office Inviting Bids | Senior Purchase And Stores Officer |
| Address | Purchase Unit-ii, Rff Area, Vssc, Isro, P.o., Trivandrum-695022 |
| Contact Details | NA |
| NA | |
| Website | NA |
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